`ifndef PIPE_DFF_V
`define PIPE_DFF_V


module pipe_dff #(
	parameter DATA_WIDTH = 32
)
(
	input  wire 						clk			,
	input  wire 						rstn		,
	input  wire 						hold_en		,
	input  wire[DATA_WIDTH - 1 : 0] 	def_data	, 
	input  wire[DATA_WIDTH - 1 : 0] 	data_i		, 
	output reg[DATA_WIDTH - 1 : 0] 		data_o	
);

always @(posedge clk) begin
	if((rstn == 1'b0) || (hold_en == 1'b1)) begin
		data_o <= def_data;
	end
	else begin
		data_o <= data_i;
	end
end	

endmodule


`endif // PIPE_DFF_V